The present invention relates to a semiconductor device and a method of operating the semiconductor device.
A semiconductor memory device includes a memory cell array which includes a plurality of memory cells. A connection relation or an arrangement method of the memory cells is varied depending on the type of semiconductor memory device. For example, in a NAND flash memory device, the memory cells are connected in series to constitute a cell string, and the cell string is connected between a bit line and a common source line.
FIG. 1 schematically illustrates a cell string 120 and a page buffer 110 connected to the cell string 120 of a NAND flash memory device in the related art, and FIG. 2 schematically illustrates a read operation of the page buffer 110 illustrated in FIG. 1.
Referring to FIGS. 1 and 2, the page buffer 110 includes a PMOS transistor MP pre-charges a sense node SO in response to a pre-charge bar signal PRECHb, an NMOS transistor MN selectively connects a bit line BL to the sense node SO in response to a bit line signal BSL, and a latch 112 temporally store data corresponding to a potential of the sense node SO. The page buffer 110 is connected to a cell string 120 through the bit line BL.
The cell string 120 includes a plurality of cell transistors MC1 to MCn. When a read voltage is applied to a word line WL2 and data stored in a selected memory cell MC2 is read, the page buffer 110 verifies the data stored in the selected memory cell MC2 as follows.
First, the sense node SO is pre-charged with a voltage PB_VREF, and then, a drain selection transistor DST, a source selection transistor SST, and the remaining cell transistors MC1 and MC3 to MCn, except for the selected cell transistor MC2, included in the cell string 120 are all turned on. Accordingly, when the selected cell transistor MC2 is turned on according to a voltage applied to the word line WL2, a current path is formed, so that a bit line current IBL flows. Particularly, when the selected memory cell MC2 is in a program state, the cell transistor MC2 is in an off state, so that a voltage level of the sense node SO is constantly maintained in the pre-charge voltage PB_VREF. When the selected memory cell MC2 is in an erase state, the cell transistor MC2 is turned on and thus a discharging current IBL flows, thereby decreasing the voltage level of the sense node SO. According to the voltage level of the sense node SO, data is stored in the latch 112.
When a voltage level of the bit line BL is decreased in the read operation, the current IBL flowing through the bit line BL, i.e., the current flowing through the selected memory cell MC2, may be decreased. As a result, there are some concerns that a threshold voltage of the selected memory cell MC2 may be verified to be larger than an actual threshold voltage, thereby finally resulting in malfunction of the semiconductor memory device.